This invention relates to a semiconductor device and, particularly, to a semiconductor device suitable for reducing the size without lowering the current capacity of transistors.
Bipolar transistors have the advantages of higher operating speed and larger current driving ability over field effect transistors. In order to further speed up the bipolar transistor operation, the transistors are dimensioned more finely in both the lateral and vertical directions. However, as a result of the reduction in the dimensions of a transistor, the "outer base region" for leading out the base terminal becomes larger than the intrinsic base region which exists beneath the emitter region and provides the essential transistor operation. The outer base region creates a larger parasitic capacitance and therefore the further speed-up of the transistor cannot be expected.
FIG. 1 shows an example of the transistor structure which overcomes the above-mentioned problem to achieve the speed-up of the transistor, and such a semiconductor structure is disclosed, for example, in Japanese Patent Unexamined Publication Nos. 56-1556 and 58-73156. In FIG. 1, the semiconductor structure includes a p-type silicon substrate 1, an n-type buried layer 2, an insulation film 3 made of silicon oxide, an n-type collector region 4, a p-type intrinsic base region 5, an outer base region 6' made of polycrystalline silicon for leading out the base terminal, an n-type emitter region 7', an emitter electrode 8', a base electrode 9', and a collector electrode 10'. In the conventional transistor structure shown in the figure, the intrinsic base region 5' has its side wall 11 connected to the outer base region 6', to which the base electrode 9 is connected. The outer base region 6' is formed on the thick insulation film 3, and therefore the parasitic capacitance between the base and collector is small. Consequently, the speed reduction due to the parasitic capacitance is prevented, and the high-speed transistor operation is accomplished.
However, in order for the transistor to have a further enhanced performance, it needs much smaller dimensions for the emitter region. Since the maximum allowable current density of the transistor cannot be changed, the reduced emitter area results in the reduction in the current capacity of the transistor. Conventionally, when the emitter width has been reduced, the emitter length has been increased to compensate for the emitter width reduction, thereby preventing a lowering of the transistor current capacity. However, it is obvious that such a conventional semiconductor structure cannot make the transistor area smaller, and this has been a barrier to the higher integration of transistors.